FIG. 1 is a split-level perspective view showing a simplified representation of a type of PLD, e.g., a Field Programmable Gate Array (FPGA) 100. Similar to most integrated circuits, FPGA 100 includes programmable circuitry formed on a semiconductor substrate that is housed in a package having externally accessible pins. In order to provide a simplified explanation of how an FPGA is configured, FPGA 100 is functionally separated into a configuration plane 120 and a logic plane 150.
Configuration plane 120 generally includes a configuration circuit 122 and configuration memory array 125. Configuration circuit 122 includes several input and/or output terminals that are connected to dedicated configuration pins 127 and to dual-purpose input/output (I/O) pins 128. Configuration memory array 125 includes memory cells, e.g., 126-1 and 126-2 that are arranged in “frames” (i.e., columns of memory cells extending the length of FPGA 100), e.g., column 140, and column addressing circuitry (not shown) for accessing each frame. JTAG (Boundary Scan) circuitry 130 is included in configuration plane 120, and is also connected to at least one terminal of configuration circuit 122. JTAG circuit 130 includes the four well-known JTAG terminals 133 (i.e., TDI, TDO, TMS, and TCK). During configuration of FPGA 100, configuration control signals are transmitted from dedicated configuration pins 127 to configuration circuit 122. In addition, a serial configuration bit stream is transmitted from either the TDI terminal of JTAG circuit 130, or from dual-purpose I/O pins 128 or a parallel configuration bitstream from the SelectMAP interface (not shown) to configuration circuit 122. During a configuration operation, configuration circuit 122 routes configuration data from the bit stream to memory array 125 to establish an operating state of FPGA 100. For self-reconfiguration and partial reconfiguration an internal control access port (ICAP) 132 is used for a first portion of the FPGA 100 to reconfigure a second portion of the FPGA 100.
Programmable logic plane 150 includes CLBs arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect resources including interconnect lines 152 and multi-way switch boxes 153 (indicated by rectangles) that are connected between the rows and columns of CLBs. During normal operation of FPGA 100, logic signals are transmitted from dual-purpose pins 128 and/or device I/O pins 155 through the IOBs to the interconnect resources, which route these signals to the CLBs in accordance with the configuration data stored in memory array 125. The CLBs perform logic operations on these signals in accordance with the configuration data stored in memory array 125, and transmit the results of these logic operations to dual-purpose pins 128 and/or device I/O pins 155. In addition to the CLBs, programmable logic plane 150 includes dedicated random-access memory blocks (BLOCK RAM) that are selectively accessed through the interconnect resources. Other programmable logic plane resources, such as clock resources, multipliers, and so forth, are omitted from FIG. 1 for brevity. Further details may be found in U.S. Pat. No. 6,204,687, filed Aug. 13, 1999, entitled “Method and Structure for Configuring FPGAs”, by David P. Schultz, et al.
FIG. 2 illustrates a simplified frame arrangement for some configuration memory cells, for example, 126-1 and 126-2, of the configuration plane 120 of FPGA 100. FIG. 2 shows six columns 214, 216, 218, 220, 222, and 224 of configuration memory cells, a frame data register (FDR) 210, and a column address decoder 212. A frame, such as in column 216 may included configuration memory cells shown in column 140 of FIG. 1. The configuration circuit 122 in FIG. 1 includes the FDR 210. The FDR 210 is a large shift register in which a frame of configuration data is serially shifted. To configure, for example, the configuration memory cells in column 216, first, the bit stream data is shifted into FDR 210; next, the column address decoder 212 will select column 216; and lastly, the contents of FDR 210 are transferred in parallel to column 216. Further details on FGPA configuration using frames are well known and can be found in, for example, the Virtex-II Pro Platform FPGA Handbook by Xilinx, Inc. of San Jose Calif., October 2002.
One disadvantage with using conventional frames in FIG. 2 to program the configuration memory cells is that as the amount of programmable logic and programmable interconnects on the PLD changes, so does the frame size, which may vary, for example, from under 1000 bits to over 10,000 bits. Thus, as the FDR length and the column lengths are variable depending upon the size of the part, the design is not very scalable.
Another disadvantage is that frames are addressable in FIG. 2 by a one-dimensional column address. For reconfiguration this means that a whole column must be changed in order to reconfigure a portion of the column. The disadvantage gets worse as the size of the part gets larger, and the columns increase in length.
Therefore, there is a need for an improved configuration design, which is scaleable, and is better for reconfiguration.